
module fifo_rw(
    input sys_clk,
    input sys_rst_n
);

wire clk_100m;        //100M时钟
wire clk_50m;        //50M时钟
wire locked;        //PLL锁定指示

wire global_rst_n;    //全局复位信号
wire rst_busy;        //复位忙标志

//FIFO读端口
wire       clkr;
wire       re;
wire       valid;
wire [7:0] dout;
wire       empty_flag;
wire       aempty_flag;
wire [6:0] rdusedw;
  
//FIFO写端口
wire       clkw;
wire       we;
wire [7:0] di;
wire       full_flag;
wire       afull_flag;
wire [6:0] wrusedw;

 
//PLL IP核，输出一个50M时钟和一个100M时钟
pll u_pll_inst0 ( 
  .refclk(sys_clk),
  .clk0_out(clk_100m),
  .clk1_out(clk_50m),
  .lock(locked)
);


//全局复位模块，以慢时钟为准，输出复位信号，用于复位除PLL以外的模块
global_rst # (
    .RESET_KEEP_CYCLE(8),            	//复位信号最小保持周期
    .BUSY_KEEP_CYCLE(60)            	//复位忙标志保持周期
)
u_global_rst_inst0 (
    .sys_clk(clk_50m),                	//时钟
    .sys_rst_n(sys_rst_n),            	//外部输入的复位信号

    .global_rst_n(global_rst_n),    	//全局复位信号
    .rst_busy(rst_busy)                	//复位忙标志
);


//写时钟
assign clkr = clk_50m;
//读时钟
assign clkw = clk_100m;

soft_fifo u_soft_fifo_inst0 (
    //复位
    .rst(global_rst_n),

	//读端口
    .clkr(clkr),
    .re(re),
    .valid(valid),
    .dout(dout),
    .empty_flag(empty_flag),
    .aempty(aempty_flag),
    .rdusedw(rdusedw),

    //写端口
    .clkw(clkw),
    .we(we),
    .di(di),
    .full_flag(full_flag),
    .afull(afull_flag),
    .wrusedw(wrusedw)
);

fifo_r u_fifo_r_inst0(
    .sys_clk(clkr),
    .sys_rst_n(global_rst_n && rst_busy),

    .re(re),
    .valid(valid),
    .dout(dout),
    .aempty_flag(aempty_flag),
    .empty_flag(empty_flag)
);

fif_w u_fif_w_inst0(
    .sys_clk(clkw),
    .sys_rst_n(global_rst_n && rst_busy),

    .we(we),
    .di(di),
    .full_flag(full_flag),
    .afull_flags(afull_flags)
);

endmodule
